1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method for a semiconductor device and, more particularly, to preferred technology to be applied to a low on-state resistance power MOSFET (insulated gate field-effect transistor) including, for example, a trench lateral power MOSFET provided with a gate electrode inside a trench which is dug into a semiconductor substrate surface, which is suitable for use with an integrated circuit that controls high currents at a high breakdown voltage such as a switching current IC, an IC for driving an automobile power system, or an IC for driving a flat panel display.
2. Description of the Related Art
The importance of power ICs with in-built power MOSFETs has risen with the rapid popularization of portable devices and advances in high-speed communication technology. It has been hoped that conventional constructions of power ICs with a lateral power MOSFET integrated into a control circuit, in which the power MOSFET element is combined with a control drive circuit, will lead to miniaturization, lower energy consumption, higher reliability, and cost reduction. The development of high-performance lateral power MOSFETs based on a CMOS process is being conducted vigorously to this end.
MOSFETs with a trench construction are known as technology for increasing the degree of integration by reducing the device pitch. The present inventor has proposed a lateral power MOSFET in which a trench construction is applied (to be referred to hereafter as “trench lateral power MOSFET) in “A Trench Lateral Power MOSFET using Self-aligned Trench Bottom Contact Holes” (IEDM '97 Digest, pages 359 to 362, 1997). FIGS. 31 through 33 illustrate the construction of this trench lateral power MOSFET, FIG. 31 being a plan view thereof. FIG. 32 illustrates the construction of a region (referred to as the “active region” in this specification) in which the source electrode and the drain electrode are connected with a semiconductor, a gate electrode is provided and current flows, and is a sectional view along the A-A line in FIG. 31. FIG. 33 illustrates the construction of a region (referred to as the “gate region” in this specification) in which gate polysilicon is deposited on a substrate surface, and is a sectional view along the B-B line in FIG. 31.
The MOSFET 202 has a construction in which a gate oxide film 22 is formed along the inner peripheral surface of a trench 21 which is formed in a p− substrate 20, gate polysilicon 23 is formed inside the gate oxide film 22, and an n+ diffusion region 29 which serves as a drain region and an n+ diffusion region 27 which serves as a source region are formed at the bottom of the trench 21 and on the outer periphery of the trench 21 respectively. The n+ diffusion region 29 (drain region) is surrounded by an n− diffusion region 28 (n− drain region) so as to enclose the lower half of the trench 21, and this n− diffusion region 28 is further surrounded by a p− diffusion region 31 which serves as a p body.
A p+ diffusion region 32 is provided on the outside of the n+ diffusion region 27 (source region), and a p base region 33 is formed therebeneath. A thick oxide film 34 is provided inside the lower half of the trench 21 so as to maintain the breakdown voltage. In FIGS. 31 through 33, the symbol 24 indicates a source electrode, symbol 25 indicates a drain electrode, symbol 26 indicates an interlayer oxide film, symbol 35 indicates a gate electrode, symbols 36 and 37 both indicate contact portions, symbol 38 indicates an n+ diffusion region, and symbols 39 and 40 both indicate interlayer oxide films. According to this trench lateral power MOSFET 202, on-state resistance is 80 mΩ·mm2 per unit area with a breakdown voltage of 80V. The device pitch is 4 μm, approximately half the device pitch of a conventional 80V breakdown voltage lateral power MOSFET
It is also desirable to apply a trench construction to a lateral power MOSFET with a lower breakdown voltage than 80V, for example 30V, in order to reduce the device pitch. Since the trench lateral power MOSFET 202 shown in FIGS. 31 through 33 is constructed to be applied to a breakdown voltage of 80V, however, the following problem occurs when applied without modification to a breakdown voltage lower than 80V. That is, when the breakdown voltage is lower than 80V, the thickness of the oxide film 34 for maintaining breakdown voltage may be thinner than that required to maintain a breakdown voltage of 80V. In other words, as long as the thickness of this oxide film 34 is set sufficiently thickly to maintain a breakdown voltage lower than 80V, the size of the entire device may be reduced. When an 80V breakdown voltage construction is applied, however, the size of an entire element grows larger than a case in which the thickness of the breakdown voltage-maintaining oxide layer 34 has been optimized, and as a result, problems occur in the characteristic of the device such as an increase in wiring resistance and the like around the element.
The gate area also grows larger than when the thickness of the breakdown voltage-maintaining oxide layer 34 has been optimized, with the result that parasitic gate capacitance rises and driving loss increases. Furthermore, in the manufacture of the aforementioned trench lateral power MOSFET 202, a shallow trench is dug and the lateral surfaces thereof are protected by a nitride film, whereupon a further, deeper trench is dug so that thermal oxidation can be performed. Thus, the manufacturing process to form the thick oxide film 34 for maintaining the breakdown voltage is complicated, which may lead to a deterioration in yield.